1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an apparatus and a method for driving a liquid crystal display device that compares a data for each line, to thereby minimize a data transition amount and improve an electromagnetic interference (EMI) characteristic.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) device controls light transmittance of liquid crystal cells in accordance with data signals applied thereto, to thereby display an image. In particular, an active matrix type LCD device includes a switching device for each cell and has various applications, such as a monitor for a computer, an office equipment, and a cellular phone, because of their high quality image, lightness, thin thickness, compact size, and low power consumption. A thin film transistor (TFT) is generally employed as the switching device for the active matrix type LCD device.
FIG. 1 is a schematic block diagram showing a driving apparatus for a liquid crystal display device according to the related art. In FIG. 1, an LCD driving apparatus includes a liquid crystal display panel 2 having liquid crystal cells Clc arranged in a matrix-like manner at intersections between data lines DL and gate lines GL, a data driver 4 for applying data signals to the data lines DL, a gate driver 6 for applying gate signals to the gate lines GL, and a timing controller 8 for controlling the data driver 4 and the gate driver 6 using signals applied from a system 10.
In addition, a thin film transistor TFT is provided at each of the liquid crystal cells Clc. The thin film transistor TFT applies a data signal from a respective one of the data lines DL to the liquid crystal cell Clc in response to a scanning signal from a respective one of the gate lines GL. A storage capacitor Cst also is provided at each of the liquid crystal cells Clc. The storage capacitor Cst maintains a voltage of the liquid crystal cell Clc.
Further, the data driver 4 converts digital video data R, G and B into analog gamma voltages, i.e., data signals, corresponding to gray level values in response to a data control signal DCS from the timing controller 8, and applies the analog gamma voltages to the data lines DL. The gate driver 6 sequentially applies a scanning pulse to the gate lines GL in response to a gate control signal GCS from the timing controller 8, to thereby select horizontal lines of the liquid crystal display panel 2 to be supplied with the data signals.
The system 10 applies vertical/horizontal synchronizing signals V and H, a clock signal DCLK and a data enable signal DE to the timing controller 8. Further, the system 10 compresses a parallel digital data into a serial data using a low voltage differential signal interface, and applies the compressed data LVDS to the timing controller 8.
Moreover, the timing controller 8 generates the gate control signal GCS and the data control signal GCS using the vertical/horizontal synchronizing signals V and H, the clock signal DCLK and the data enable signal DE inputted from the system 10. The timing controller 8 also restores the compressed data LVDS from the system 10 into a parallel data and supplies the restored data data to the data driver 4.
For example, for each pixel, the timing controller 8 applies 18 bit data, each of R, G and B data having 6 bits, to the data driver 4 using 18 data lines. As shown in Table 1, if all of the current pixel data Pn have bits of ‘0’ while all of the next pixel data Pn+1 have bits of ‘1,’ such a transition for all bits causes a high EMI.
TABLE 1R[0:5]G[0:5]B[0:5]Pn000000000000000000Pn + 1111111111111111111
In particular, such a phenomenon becomes more serious as a resolution and a dimension (i.e., inch) of the liquid crystal display panel 2 become larger. For instance, if 24 bits are used for data for one pixel where each R, G and B data having 8 bits, then the number of bits transferred from the timing controller 8 into the data driver 4 is increased to cause an even higher EMI. Accordingly, a serious EMI occurs due to a transition of the data.
FIG. 2 is a schematic block diagram showing another driving apparatus for a liquid crystal display device according to the related art. In particular, the driving apparatus shown in FIG. 2 has been suggested to reduce a high EMI as discussed with respect to the apparatus shown in FIG. 1. As shown in FIG. 2, an LCD driving apparatus includes a liquid crystal display panel 2 having liquid crystal cells Clc arranged in a matrix-like manner at intersections between data lines DL and gate lines GL, a data driver 4 for applying data signals to the data lines DL, a gate driver 6 for applying gate signals to the gate lines GL, and a timing controller 12 for controlling the data driver 4 and the gate driver 6 using signals applied from a system 10.
The timing controller 12 generates a gate control signal GCS and a data control signal GCS for controlling the gate driver 6 and the data driver 4, respectively, using vertical/horizontal synchronizing signals V and H, a clock signal DCLK and a data enable signal DE inputted from the system 10. Although not shown, the gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE, and the data control signal DCS includes a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE and a polarity control signal POL. The timing controller 12 also compressed data LVDS from the system 10 into a parallel data and supplies the restored data data to the data driver 4. The timing controller 12 further includes a mode controller 14 for minimizing a transition frequency of data.
In particular, the mode controller 14 compares data transition states between the next pixel data and the current pixel data. Thus, the mode controller 14 compares each bit of the next pixel data Pn+1 with each bit of the current pixel data Pn to detect a bit transition amount such as “0→1” or “1→0”, and makes an inverted or non-inverted output of the data in response to the detected bit transition amount.
In addition, the mode controller 14 counts bit transition amounts between the current pixel data Pn and the next pixel data Pn+1, and checks whether or not the counted transition amount exceeds a critical value. For instance, the critical value could be 9, a half of an 18 bit data. Then, as shown in Table 2, whenever the data transition amount exceeds the critical value, the mode controller 14 inverts a logical value of a mode control signal REV and inverts the next pixel data to be supplied.
TABLE 2R[0:5]G[0:5]B[0:5]Bit transition amountREVPn000000000000000000 0lowPn + 111111111111111111116highPn + 1′000000000000000000n/an/a
For instance, if all of the current pixel data Pn have bits of ‘O’ while all of the next pixel data Pn+1 have bits of ‘1,’ the mode controller 14 counts the bit transition amount to be 16. Since the bit transition amount is more than the critical value of 9, the mode control signal REV is inverted and an inverted next pixel data Pn+1' having “000000 000000 000000” is generated and applied to the data driver 4 as the next frame data. That is, all bits of the next pixel data Pn+1 are inverted in response to the mode control signal REV, thereby sending the inverted next pixel data Pn+1' which has the same bits as the previous frame data to the data driver 4.
FIG. 3 is a block diagram showing a data integrated circuit according to the related art. As shown in FIG. 3, the data driver 4 (shown in FIG. 2) includes a data integrated circuit (IC) having a data restoration part 18, a shift register part 20, a latch part 22, a digital to analog converter (DAC) part 24 and an output buffer part 26. The data restoration part 18 inverts or non-inverts a data in response to the mode control signal REV prior to applying the data to the latch part 22. In particular, when the mode control signal REV is inverted, the data restoration part 18 inverts all bits of a data supplied thereto to generate a restored data and applies the restored data to the latch part 22. When the mode control signal REV is not inverted, the data restoration part 18 relays a data supplied thereto to the latch part 22.
In addition, the shift register part 20 includes a plurality of shift registers to sequentially shift the source start pulse SSP from the timing controller 12 in response to the source shift clock SSC, thereby outputting a sampling signal. The latch part 22 then sequentially samples a data data supplied from the data restoration part 18 in response to the sampling signal from the shift register part 20 and then latches it. In particular, the latch part 22 has i latches (i being an integer), and each of the latches has a size corresponding to the bit number of data (e.g., 6 bits or 8 bits). Further, the latch part 22 simultaneously outputs the latched i data in response to the source output enable signal SOE supplied from the timing controller 12.
The DAC part 24 converts the latched data received from the latch part 22 into positive and/or negative data signals. In particular, the DAC part 24 receives a plurality of gamma voltages from a gamma voltage generator (not shown) and converts the latched data into positive and/or negative data signals in response to the polarity control signal POL. Then, the DAC part 24 outputs the converted data to the output buffer part 26. The output buffer part 26 buffers the converted data and applies the buffered data to the data lines DL.
Although in comparison to the driving apparatus shown in FIG. 1, the driving apparatus shown in FIG. 2 compares the current pixel data with the next pixel data to reduce a generation of high EMI, the driving apparatus shown in FIG. 2 has a limit in reducing the bit transition frequency of data because the apparatus only compares the current pixel data and the next pixel data with each other.